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・ Dynamic stereochemistry
・ Dynamic Stillness
・ Dynamic stochastic general equilibrium
・ Dynamic stock modelling
・ Dynamic strain aging
・ Dynamic stretching
・ Dynamic structure factor
・ Dynamic Structures
・ Dynamic synchronous transfer mode
・ Dynamic systems development method
・ Dynamic Tension
・ Dynamic Terrain
・ Dynamic testing
・ Dynamic tidal power
・ Dynamic time warping
Dynamic timing verification
・ Dynamic Togolais
・ Dynamic tonality
・ Dynamic topic model
・ Dynamic topography
・ Dynamic Tower
・ Dynamic treatment regime
・ Dynamic trimming
・ Dynamic Trunking Protocol
・ Dynamic Twins
・ Dynamic unobserved effects model
・ Dynamic update client
・ Dynamic vapor sorption
・ Dynamic verb
・ Dynamic Vibration Absorber


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Dynamic timing verification : ウィキペディア英語版
Dynamic timing verification
Dynamic timing verification refers to verifying that an ASIC design is fast enough to run without errors at the targeted clock rate. This is accomplished by simulating the design files used to synthesize the integrated circuit (IC) design. This is in contrast to static timing analysis, which has a similar goal as dynamic timing verification except it does not require simulating the real functionality of the IC.〔"ASIC world: vol 10", page 13, October 2003〕
Hobbyists often perform a type of dynamic timing verification when they over-clock the CPUs in their computers in order to find the fastest clock rate at which they can run the CPU without errors. This is a type of dynamic timing verification that is performed after the silicon is manufactured. In the field of ASIC design, this timing verification is preferably performed before manufacturing the IC in order to make sure that IC works under the required conditions before mass production of the IC.〔
==References==


抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
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